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CDB61584A
Product Databook
FEATURES
s Socketed CS61584A Dual Line Interface s All Required Components for CS61584A Evaluation s Locations to Evaluate Protection Circuitry s LED Status Indications for Alarm Conditions s Support for Hardware and Host Modes
Dual Line Interface Unit
DESCRIPTION
The evaluation board includes a socketed CS61584A dual line interface device and all support components necessary for evaluation. The board is powered by an external +5 Volt supply. The board may be configured for 100 twisted-pair T1, 75 coax E1, or 120 twisted-pair E1 operation. Binding posts and bantam jacks are provided for line interface connections. Several BNC connectors provide clock and data I/O at the system interface. Reference timing may be derived from a quartz crystal, crystal oscillator, or an external reference clock. Four LED indicators monitor device alarm conditions.
5V+ 0V
ORDERING INFORMATION: CDB61584A
TCLK1 TPOS1 (TDATA1) TNEG1 CHANNEL 1 RCLK1 RPOS1 (RDATA1) RNEG1 (BPV1)
TTIP1
TRING1 RTIP1 CHANNEL 1
RRING1 RESET CIRCUIT
V+ Hardware Control and Mode Circuit LED Status Indicators Serial Interface Control Circuit TCLK2 TPOS2 (TDATA2) TNEG2 CHANNEL 2 RCLK2 RPOS2 (RDATA2) RNEG2 (BPV2)
CS61584A
REFCLK
XTL
Oscillator Circuit
TTIP2
TRING2 RTIP2 CHANNEL 2
RRING2
DS261DB2
Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved)
MAR `98
CDB61584A
Dual Line Interface Unit
POWER SUPPLY
As shown on the evaluation board schematic in Figures 1-5, power is supplied to the board from an external +5 Volt supply connected to the two binding posts labeled V+ and GND. Zener diode Z1 protects the components on the board from reversed supply connections and over-voltage damage. Capacitor C16 provides power supply decoupling and ferrite bead L1 helps isolate the CS61584A and buffer supplies. Both sides of the evaluation board contain extensive areas of ground plane to insure optimum performance. Capacitors C3, C5-C8, C13, C18, and C38 provide power supply decoupling for the CS61584A. The BGREF pin is pulled down through resistor R10 to provide an internal current reference. The buffers are decoupled using capacitors C9, C15, and C19. Ferrite beads L2-L4 help reduce the power supply noise that is coupled from the buffers to the power supply.
-
TAOS1, TAOS2: transmit all ones; LLOOP: local loopback of both channels; RLOOP1,2: remote loopback 1,2; PD1, PD2: power down; ATTEN0, ATTEN1: jitter attenuator selection; CLKE: RCLK edge polarity; 1XCLK: clock frequency selection; CONx1, CONx2: line configuration settings.
All switch inputs are pulled-down using resistor networks RP2-RP5. The LOS1 and LOS2 LED indicators illuminate when the line interface receiver has detected a loss of signal. Headers J7 and J13 must be jumpered in the "TNEG" position to provide connectivity to the BNC input in Hardware mode.
Host Mode
In Host mode operation, the evaluation board supports serial-port operation over interface port J26 using the printer port of a host PC equipped with the enclosed software. The evaluation board is connected to the host PC using the ribbon cable provided. The SW2 switch position labeled "ATTEN0" must be open to set the P/S pin of the CS61584A to a logic 0 and enable serial-port operation. An external microprocessor may also interface to the evaluation board for the purposes of system software development. The CS61584A interrupt pin is connected to pin 23 of interface port J26 to facilitate software development. The SW2 switch position labeled "CLKE/IPOL" establishes the polarity of the interrupt pin. If an active low interrupt is selected (IPOL low), the interrupt pin must be pulled-up through resistor R55 by placing a jumper on header J24. The SW2 switch position labeled "RLOOP1" must be in the open position for proper operation of the interrupt. The LOS1 and LOS2 LED indicators illuminate when the line interface receiver has detected a loss of signal. If coder mode is enabled in the CS61584A register set, the AIS alarm condition is
BOARD CONFIGURATION
Slide switch SW6 selects hardware or host mode operation. Hardware mode is selected when switch SW6 is in the "HW" position and sets the MODE pin of the CS61584A to a logic 0. Host mode is selected when switch SW6 is in the "SW" position and sets the MODE pin of the CS61584A to a logic 1.
Hardware Mode
In Hardware mode operation, the evaluation board is configured using DIP switches SW2, SW3, and SW4. In this mode, the switches establish the digital control inputs for both line interface channels. Closing a DIP switch towards the label sets the CS61584A control pin of the same name to a logic 1. The host processor interface J26 should not be used in the Hardware mode. The CDB61584A switches and functions are listed below:
52
DS261DB2
CDB61584A
Dual Line Interface Unit provided when headers J7 and J13 are jumpered in the "AIS" position. The AIS1 and AIS2 LED indicators illuminate when the line interface receiver has detected the all-ones receive input signal. Resistors R26 and R27 pull-down the TNEG(1,2) inputs when coder mode is disabled but headers J7 and J13 are jumpered in the "AIS" position. Further details concerning Host mode operation are described in the "readme.txt" file on the enclosed disk. pacitor is required for 100 twisted-pair T1 or 120 twisted-pair E1 applications. A 470 pF capacitor is required for 75 coax E1 applications. These capacitors are included with the evaluation board. Optional diode locations D6-D9 and D10-D13 and optional resistor locations R8-R9 and R18-R19 provide test locations to evaluate transmit line interface protection circuitry.
RECEIVE CIRCUIT
The receive signal is input at either the RTIP(1,2) and RRING(1,2) binding posts or the RX(1,2) bantam jacks. The receive signal is transformer coupled to the CS61584A through 1:1.15 step-down transformers T2 and T3. The receive line is terminated by resistors R3-R4 and R14-R15 to provide impedance matching and receiver return loss. They are socketed so the values may be changed according to the application. The evaluation board is supplied from the factory with 38.3 resistors for terminating 100 twistedpair T1 lines, 45.3 resistors for terminating 120 twisted-pair E1 lines, and 28.7 resistors for terminating 75 coaxial E1 lines. Capacitors C4 and C10 provide a differential input voltage reference. Optional resistor locations R1-R2, R12-R13, R16R17, and R24-R25 provide test locations to evaluate receive line interface protection circuitry. The recovered clock and data signals are available on BNC outputs labeled RCLK(1,2), RPOS(1,2), and RNEG(1,2). In Hardware and Host mode (with coder mode disabled), data is available on the RPOS(1,2) and RNEG(1,2) BNC outputs in RZ format. In Host mode with coder mode enabled, data is available on the RDATA(1,2) BNC output in NRZ format and bipolar violations are reported on BPV(1,2).
Manual Reset
A momentary contact switch SW1 provides a manual reset by forcing the RESET pin of the CS61584A to a logic 1. Although the transmit and receive circuitry are continuously calibrated, the reset can be used to initialize the control logic and clear the register set. Both channels are powered up after exiting reset.
TRANSMIT CIRCUIT
The transmit clock and data signals are supplied on BNC inputs labeled TCLK(1,2), TPOS(1,2), and TNEG(1,2). In Hardware and Host mode (with coder mode disabled), data is supplied on the TPOS(1,2) and TNEG(1,2) BNC inputs in RZ format. In Host mode with coder mode enabled, data is supplied on the TDATA(1,2) BNC input in NRZ format and the TNEG(1,2) BNC input may be used to indicate the AIS alarm condition as described in the Host Mode section. The transmitter output is transformer coupled to the line interface through 1:1.15 step-up transformers T1 and T4. The signal is available at either the TTIP(1,2) and TRING(1,2) binding posts or the TX(1,2) bantam jacks. Capacitors C2 and C11 prevent output stage imbalances from producing a DC current that may saturate the transformer and result in an output level offset. Capacitors C1 and C12 provide transmitter return loss and are socketed so the value may be changed according to the application. A 220 pF caDS261DB2
53
CDB61584A
Dual Line Interface Unit
REFERENCE CLOCK
The CDB61584A requires a T1 or E1 reference clock for operation. This clock may operate at either a 1-X rate (1.544 MHz or 2.048 MHz) or an 8X rate (12.352 MHz or 16.384 MHz) and can be supplied by either a quartz crystal, crystal oscillator, or external reference. The evaluation board is supplied from the factory with two crystal oscillators for T1 and E1 operation.
JTAG ACCESS
The CS61584A implements JTAG boundary scan to support board-level testing. Interface port J56 provides access to the four JTAG pins on the CS61584A. The J-TMS pin of the CS61584A is pulled-down by resistor R28 to disable boundary scan unless the pin is externally pulled high using the interface port.
TRANSFORMER SELECTION
The evaluation board is supplied from the factory with Pulse Engineering PE-65388 transformers installed at locations T1-T4. They are socketed to permit the evaluation of other transformers.
Quartz Crystal
A quartz crystal may be inserted at socket Y1. Because the crystal operates at an 8-X rate, the SW2 switch position labeled "1XCLK" must be open to set the 1XCLK pin of the CS61584A to a logic 0 and enable 8-X clock operation.
LINE PROTECTION EVALUATION
Several optional resistor and diode locations on the transmit and receive line interface allow for the installation and evaluation of various types of protection circuitry. Each location is drilled with 60 mil vias to permit the installation of sockets. These sockets can be obtained from McKenzie at (510) 651-2700 by requesting part #PPC-SIP-1X32620C and are identical to the socket type installed at the receive resistor locations on the board. They allow the line protection circuitry to be easily changed during testing. Note that the traces forming shorts between the socket locations on the line interface may need to be cut prior to the installation of protection circuitry.
Crystal Oscillator
A crystal oscillator may be inserted at socket U4 in the orientation indicated by the silkscreen. Header J14 must be jumpered in the "OSC" position to provide connectivity to the REFCLK pin of the CS61584A. The SW2 switch position labeled "1XCLK" must be open (logic 0) for 8-X clock operation or closed (logic 1) for 1-X clock operation.
External Reference
An external reference may be provided at the REFCLK BNC input. Header J14 must be jumpered in the "REFCLK" position to provide connectivity to the REFCLK pin of the CS61584A. The SW2 switch position labeled "1XCLK" must be open (logic 0) for 8-X clock operation or closed (logic 1) for 1-X clock operation.
PROTOTYPING AREA
Four prototyping areas with power supply and ground connections are provided on the evaluation board. These areas can be used to develop and test a variety of additional circuits such as framer devices, system synchronizer PLLs, or specialized interface logic.
BUFFERING
Buffers U2, U3, and U6 provide additional drive capability for the BNC and Host mode connections. The buffer outputs are filtered with an RC network to reduce the transients caused by buffer switching.
54
DS261DB2
CDB61584A
Dual Line Interface Unit
EVALUATION HINTS
1) The orientation of pin 1 for the CS61584A is labeled "1" on the left side of the socket U7. 2) A jumper must not be placed on header J10 when using the CDB61584A. 3) Component locations R3-R4, R14-R15, C1, and C12 must have the correct values installed according to the application. All the necessary components are included with the evaluation board. 4) Closing a DIP switch on SW2, SW3, and SW4 towards the label sets the CS61584A control pin of the same name to logic 1. 5) When performing a manual loopback of the recovered signal to the transmit signal at the BNC connectors, the recovered data must be valid on
the falling edge of RCLK to properly latch the data in the transmit direction. To accomplish this, the SW2 switch position labeled "CLKE" must be closed (logic 1) during Hardware mode operation or the CLKE bit in the Control A register must be set to a 1 during Host mode operation. 6) Jumpers can be placed on headers J9 and J12 to provide a ground reference on TRING for 75 coax E1 applications. 7) Properly terminate TTIP/TRING when evaluating the transmit output pulse shape. For more information concerning pulse shape evaluation, refer to the Crystal application note entitled "Measurement and Evaluation of Pulse Shapes in T1/E1 Transmission Systems."
DS261DB2
55
CDB61584A
Dual Line Interface Unit
J1 R29
L4 3 U2 C26 100pF 5 U2 C27 100pF 7 U2 13 15 17
VA+
RCLK1 51.1
J2 RPOS1 (RDATA1) R30
C9
20 10
.1F
VCC 1 U2 19
GND
ENA ENA
51.1 J3
R31
RNEG1 (BPV1)
51.1 J4
4
C28 100pF 16 U2 C29 100pF 14 U2 C30 100pF U2 R5 1 3 J7 2 4 J-TDO 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 U7 CS61584A CHANNEL 1 RCLK1 RPOS1 RNEG1 TCLK1 TPOS1 TNEG1 LOS1 J-TDO DGND2 J-TDI TTIP1 TV+1 TGND1 TRING1 PD1 ATTEN0 N/C-1
TCLK1
J5 TPOS (TDATA1) J6 TNEG
8 6
AIS1
D1 LED LOS1 D2 LED R7 R6
12 C31 100pF VA+ 3 2 Q1 1 3 Q2 1
R38 R39
51.1 51.1
51.1
VD+
R26 47K C3
J-TDI
470
VA+
2
.1F
PD1
ATTEN0
VD+
470
TTIP1
J31
T R
J8A 1 4
R8 R9
1 3
T1
D10 2
VD+
D12
D11
C1
27 RTIP1 28 RRING1
TRING1
J32 J9
5 6 1.15:1 PE -65388
TV+1
C2 D13
.47F
RTIP1
J33
T
J8B 6 R 9
R24
1 3
T2
2
R1
R25
RRING1
J34
6 1.15:1 PE -65388
5
R2 R4 R3
C4 .47F
Notes: Components R3, R4, and C1 are socketed to permit value changes to the application. Component locations R1, R2, R8, R9, R24, R25, and D10-D13 provide areas for evaluating protection circuitry.
Figure 1. Channel 1 Circuitry
56
DS261DB2
CDB61584A
Dual Line Interface Unit
VA+ 11 L2 U3 9 C32 100pF 7 U3 C15 C33 100pF
J16 R41 RCLK2
51.1
J17 R42 51.1 J18 R43
ENA
VCC 1 20 ENA 19 U3 10 GND
13
RPOS2 (RDATA2)
.1F
15 5 U3 C34 100pF 14 6
51.1
J19
RNEG2 (BPV2)
U7 CS61584A CHANNEL 2
100pF
N/C-3 60
U3 C35
TCLK2
J20
RCLK2 RPOS2 RNEG2 TCLK2 TPOS2 TNEG2 LOS2 CON32 J-TCK J-TMS TTIP2 TV+2 TGND2 TRING2 PD2 CLKE
41 RRING2 42 RTIP2 43 N/C-2
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
16
U3 C36 100pF
4
TPOS2 (TDATA2) J21
R50 R51
51.1 51.1
1 3 CON32 J-TCK J-TMS VD+ R28 C13 2 R22 4 51.1
18
J13
R27 47K
U3 C37 100pF VA+ 3 2 Q3 1 R20 470 3
2
TNEG2
AIS2 D3 LED
10K
VA+
.1F PD2 CLKE VD+
D6 2 C12 2
Q4 1 R21 470
LOS2
D4 LED
T4
1 3
R18 R19
6 J11B 9
J27
TTIP2
VD+
D7 D8 6
T
R J28
TV+1
C38 22F C11
.47F
D9 R12
5 1:1.15 PE-65388
TRING2
J12
2
T3
1 3
R16
1 J11A
J29 T R J30
RTIP2
R13 R14 R15
6
5
R17
4
1:1.15 PE-65388
RRING2
C10
.47F
Notes: Components R14, R15, and C12 are socketed to permit value changes according to the application. Component locations R12, R13, R16-R19, and D6-D9 provide areas for evaluating protection circuitry.
Figure 2. Channel 2 Circuitry
DS261DB2
57
CDB61584A
Dual Line Interface Unit
VD+ J24
R55 3.92k
CS SD1 SCLK
SD0 25 INT 23 21 19 17 15 13 11 9 7 5 3 1
J26
26 24 22 20 18 16 14 12 10 8 6 4 2
R56 51.1 R40 51.1 100 pF C25 U6 9 GND 100 pF 7 C39 U6 13 GND J-TD0 J-TD1 J-TMS T-TCK 1 3 5 7
J56
2 4 6 8
11 RP2 1 47k
VD+
SW2 24 23 22 21 20 19 18 17 16 15 14 13 TAOS2 TAOS1 LLOOP RLOOP2 RLOOP1 PD1 PD2 ATTEN0 ATTEN1 CLKE/IPOL 1XCLK
8 7 6 5 4 32 8 7 6 5 4 32
1 2 3 4 5 6 7 8 9 10 11 12
6 5 43 2
CON01 CON11 CON21 CON31
VD+ SW3 1 8 2 7 3 6 4 5
PD1 PD2 ATTEN0 CLKE/IPOL 1XCLK
SW4 CON02 1 8 CON12 2 7 CON22 3 6 CON32 4 5 CON32
1 RP4 47k GND RP5 47k
1 6 5 43 2 GND RP3 U6 C24 100 16 100pF 100pF 14 18 pF C23 C20 51.1 R57 R58 51.1 6 U6 2 U6 4 VD+ .01F C18 1 47k
Figure 3. Control Circuitry
58
N/C-4 ATTEN1 RLOOP1 RLOOP2 LLOOP TAOS1 TAOS2 CON01 DGND1 DV+ DGND3 CON02 CON11 CON12 CON21 CON22 CON31
U7 CS61584A CONTROL CIRCUITRY
5 4 3 51.1 R59 2 1 68 67 66 65 64 63 62 61
9 8 7 6
DS261DB2
CDB61584A
Dual Line Interface Unit
U7 CS61584A TIMING CIRCUITRY 29 RV+1 30 RGND1 31 MODE 32 R10 BGREF 4.99k 33 AGND 34 AV+ 35 RESET 36 REFCLK 37 XTALOUT 1XCLK 38 1XCLK 39 RGND2 40 RV+2 Y1
C5
.1F
C8
.1F
VD+
.1F 1.0F
C6 C7
VD+ J 10 (must not be jumped)
VD+ SW6
SW1 2 R23 47K 1 R11 10K
VD+
VD+
VA+ U4
C14 .1F VCC GND 8
24
J14 REFCLK
13
J15
Figure 4. Timing Circuitry
DS261DB2
59
CDB61584A
Dual Line Interface Unit
V+
J22 VA+
GND J23
C16 47F
Z1 VD+ L1
VD+
Prototyping Area
Figure 5. Common Circuitry
60
DS261DB2
* Notes *
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

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